SpacemiT launches V100, a 46-core RISC-V server CPU
SpacemiT launched the 46-core RISC-V server CPU V100 on October 19: eight DDR5 channels, 120W and a full server-spec compliance claim. No price or ship date.
SpacemiT is a Chinese company that designs RISC-V processors. On October 19, at the sixth RISC-V China Summit in Shenzhen, it launched the V100, a server-class CPU with 46 cores: six XiangShan Kunminghu V2R2 cores and forty of its own X100 cores. The company calls it the first chip that fully complies with the RISC-V server specification. None of the coverage we read includes a third-party benchmark, so the most useful part of the launch is the product documentation. It lists firmware, boot and security requirements as items a buyer can check one by one.
Key points
- Cores and clocks: six V2R2 cores up to 2.1 GHz and forty X100 cores up to 2.4 GHz. SpacemiT’s own per-GHz SPECint2006 figures are at least 15.0 and 9.0.
- Memory and I/O: eight DDR5-4800 channels with 307 GB/s peak bandwidth, 52 PCIe 5.0 lanes and a 120 W TDP.
- Systems: three servers launched with the chip: the C2201 compute server, the G5201 AI server and the S5236 storage server. Neither price nor availability has been announced.
Background
The numbers have moved since January 2025. A SpacemiT press release dated January 8, 2025 described the X100 core as delivering more than 9 points per GHz on SPECINT2006 “at 2.5GHz@12nm.” It also listed a “64-core interconnect” among the core’s features, and said platform firmware and Linux had run on an FPGA prototype. That month, Heise Online reported the chip as a server processor with up to 64 RISC-V cores, and Tom’s Hardware repeated the figure. This year’s product documentation lists 46 cores, a 2.4 GHz top clock for X100, and no process node. Hardware Busters notes that SpacemiT has not explained the change.
For context on RISC-V chip companies in public markets, ESWIN Computing’s Hong Kong listing on October 9 made it the first HKEX company whose main business is RISC-V chips.
Specs and systems
SpacemiT’s product documentation gives these figures.
| Item | Figure in product documentation |
|---|---|
| Cores | 6 × XiangShan Kunminghu V2R2 + 40 × X100 = 46 cores, RVA23 Profile |
| Clocks and per-GHz score | V2R2 up to 2.1 GHz, SPECint2006 at least 15.0/GHz; X100 up to 2.4 GHz, at least 9.0/GHz (vendor figures) |
| Cache | 64 MB SLC |
| Memory | 8 DDR5 channels, 1DPC, DDR5-4800, 307 GB/s peak; up to 256 GB per DIMM and 2 TB per chip |
| PCIe | PCIe 5.0, 52 lanes: three 16-lane groups (x16, x8x8 or x8x4x4) plus one 4-lane group (x2x1x1) |
| Power and package | 120 W TDP; 0 to 40 °C operating range; FCBGA, 58.5 × 75.4 mm, 0.94 mm pitch |
| Virtualization and security | Hypervisor 1.0, AIA and IOMMU; root of trust and secure boot; AES, SHA, RSA, SM2, SM3, SM4 |
| Firmware and OS | UEFI 2.11, ACPI 6.6, EDK2 and openBMC; Linux kernel 6.6 and later |
| Not stated in the documents | Process node, dual-socket configuration, price, ship date |
The figures check out against each other. Eight channels of DDR5-4800 at 8 bytes per transfer give 307.2 GB/s, which matches the stated peak. A 256 GB DIMM on each channel gives 2 TB. Three 16-lane groups plus one 4-lane group add up to 52 lanes. That shows the documents are internally consistent. It does not show how the chip performs under load.
The server designs appear in press coverage, not in SpacemiT’s chip documentation. Science and Technology Daily reports that the G5201 AI server takes eight double-width accelerator cards and has been verified with Kunlunxin’s M100. It also reports that SpacemiT supplies motherboards, firmware, BMC management and hardware reference designs, so partners need less board development from scratch. LinuxGizmos, relaying the specifications, says the C2201 compute server runs in single- or dual-socket form. Its dual-socket configuration reaches 92 cores, 4 TB of memory and 88 PCIe 5.0 lanes.
What others say
Phoronix’s coverage argues that the 46-core, 12nm chip, pitched at servers during the AI boom, is not as advanced as current Intel Xeon or AMD EPYC x86 processors, or even Arm server CPUs. The article says it hopes to benchmark real hardware.
Hardware Busters goes further. It argues that a 12nm process with DDR5-4800 memory and 2.4 GHz clocks leaves the chip generations behind current x86 and Arm server silicon. It also notes that the performance figures are SpacemiT’s own per-GHz SPECint2006 numbers, from a suite SPEC retired years ago, and that no full-chip SPECrate result or independent benchmark exists yet.
LinuxGizmos focuses on software. Relaying SpacemiT, it says the platform passed architecture, SoC and firmware compliance tests, including a UEFI Self Certification Test tied to BRS-I. Science and Technology Daily’s summit report lists supported distributions including openEuler, openRuyi, openKylin, Debian, Ubuntu, Fedora, Red Hat and Rocky. SpacemiT’s English product documentation names openEuler, openKylin, Ubuntu, Debian and Fedora, plus Kylin as a planned addition.
The reports disagree in three places. Phoronix gives clocks of 2.2 to 2.4 GHz, where the documentation and other outlets say 2.1 and 2.4 GHz. The 12nm node appears in Phoronix, LinuxGizmos and Hardware Busters, but not in SpacemiT’s documentation. The 92-core dual-socket figure appears in Phoronix and LinuxGizmos, and Hardware Busters repeats Phoronix’s number. IT Home says only that the chip allows dual-socket coherent interconnect, and the official chip documentation does not mention dual sockets. InfoQ China reported the summit and the compliance claim without independent checks.
Our take
For most readers this is not a product they can buy yet. The coverage and documents we read give no price, no ship date, no customer list and no third-party benchmark. What the launch does give readers is a spec sheet they can check and a claim they can test: that V100 is the first chip to fully comply with the RISC-V server specification. That claim is worth something only if UEFI, ACPI and BRS let mainstream distributions install and boot on real boards without custom work. RISC-V software teams should test exactly that. Server makers should watch whether anyone builds on the C2201, G5201 and S5236 designs.
Microsoft’s Maia 300 is a different kind of chip. It is an inference accelerator, and its headline comparison is with mainstream GPU systems. V100 is a host CPU, so it belongs in comparisons with x86 and Arm server processors, and no like-for-like numbers exist yet.
Three things remain open. The compliance claim is SpacemiT’s own, and we found no independent test report or certification record. SpacemiT has not explained why the 64-core figure from 2025 coverage has become 46 cores. Clock figures differ across outlets, and the documentation says nothing about the process node or dual sockets, so those numbers should be read as press reports.
What to watch
- Price and first customers: not announced, and no server makers are named.
- Third-party tests: no full-chip SPECrate or system benchmark yet. Phoronix says it hopes to get hardware for testing.
- Official wording: if SpacemiT explains the 64-to-46 change or adds a process node to its documents, these figures need updating.
CEO Chen Zhijian told the summit that SpacemiT plans to keep releasing a new chip generation every year, according to InfoQ China. To check the figures yourself, SpacemiT’s V100 product brief is a three-page PDF.