Micron skips 4F² DRAM entirely, splitting with Samsung and CXMT on the road to 3D memory
Micron CTO Scott DeBoer called 4F² density gains "a bit of a myth" on Oct 21, pulling the design from the roadmap against Samsung, SK hynix and CXMT.
On October 21, Micron’s president and chief technology and products officer Scott DeBoer did something DRAM makers rarely do in public: he took a cell architecture off the roadmap. At the company’s Technology and Product Leadership Webinar, DeBoer said 4F² DRAM — a design Micron itself invented and spent roughly two decades evaluating — would not be pursued, because “it’s a bit of a myth that 4F² actually provides anything versus 6F². It’s capacitor pitch that defines the DRAM.” With that sentence, the last of the big three DRAM makers to hedge on the question picked a side, splitting with Samsung, SK hynix and China’s CXMT, all of which are still pushing 4F².
Key points
- DeBoer said on October 21 that 4F² density gains over 6F² are “a bit of a myth”: bit density is set by capacitor pitch, not the cell layout, and 4F² scaling hits “fundamental problems” that will eventually hand the baton to 3D DRAM.
- Micron’s plan instead: 1δ volume production in H2 2027 with a mid-20% bit density gain, wafer bonding at 1ε, and High-NA EUV at the ζÅ/ηÅ sub-10nm-class nodes, with 3D DRAM as a parallel path of undated timing.
- The split is public: per TechInsights, Samsung and SK hynix still have 4F² in their roadmaps, and CXMT’s president has announced a 4F² server DDR5 RDIMM for the end of 2026.
Background
The numbers in 4F² and 6F² describe how much silicon area one DRAM cell occupies. Every DRAM in volume production today is 6F² — a cell spanning six F-widths; 4F² tucks the transistor underneath the capacitor, shrinking the cell by about a third in exchange for harder, costlier manufacturing. DeBoer’s argument is that the exchange is a bad trade: no matter how small the transistor gets, the capacitor pitch is what sets bit density, so the headline cell-size win never fully shows up as density.
CXMT is the direct context. In mid-October, its president Cao Kanyu announced a 4F² server DDR5 RDIMM with vertically gated transistors for the end of the year; Micron’s statement landed about ten days later. Micron is no newcomer to the technology, either — “Micron invented 4F² DRAM,” DeBoer said, and the company built prototypes over two decades before declining to industrialize them.
There is also a precedent for reading Micron’s public stance loosely. The company was the last of the big three to adopt EUV lithography — it first said it had no EUV plans, then prepaid ASML and moved — yet per Tom’s Hardware it stayed cost- and performance-competitive anyway. Whether the 4F² refusal is the same play in reverse is one of the open questions of this story.
The facts
DeBoer’s case has three layers, all from the webinar record. First, density follows capacitor pitch, and 4F² shrinks the transistor rather than the capacitor. Second, further 4F² scaling is blocked by physics: “There are fundamental problems with 4F² scaling, that ultimately will lead to 3D DRAM coming in instead of 4F².” Third, after roughly twenty years of evaluation Micron chose not to industrialize the design because the scaling path “is not viable beyond a certain point” and complexity and cost rise — though he granted that the cells “can be built back a few nodes, no question about it.”
Micron’s alternative route, as compiled from TrendForce’s October 22 and Tom’s Hardware’s October 26 reports:
| Node | Timing | What it brings |
|---|---|---|
| 1γ | In HVM now | First EUV node; underpins key products for the next 12 months |
| 1δ | H2 2027 | Mid-20% bit density gain; performance tuned for HBM5, vHBM and vEIM |
| 1ε | In development | Introduces wafer bonding |
| ζÅ / ηÅ | Early development | First sub-10nm-class nodes; High-NA EUV plus new materials |
| 3D DRAM | Parallel path | Listed between 1ζ and 1η; timing set by cost, complexity and performance |
3D DRAM appears on the roadmap as two generations, 3D1 and 3D2, but DeBoer called it in practice “a parallel path” — Micron will switch when it wins on cost, complexity and device performance, and not before. He acknowledged DRAM is “nearing atomic limits” while expressing confidence in several more planar nodes.
The financial footing behind the decision: Micron’s fiscal Q4 2026 (quarter ended September 3) booked $54.2 billion in revenue at an 86.8% gross margin per stockanalysis.com, the company’s most profitable quarter on record — which buys the freedom to choose the smoother, more expensive route.
What others say
The competitive picture is three against one. Tom’s Hardware cites market research firm TechInsights: both Samsung and SK hynix still carry 4F² cells in their roadmaps, leaving Micron on a unique trajectory. CXMT’s plan is the most concrete — a 4F² server DDR5 RDIMM by year-end.
The article’s own interpretation is more restrained: DeBoer’s framing that a vendor must choose between 4F² and more sophisticated process technologies “perhaps implies why” CXMT favors the former. The sharper takes circulating about CXMT — no access to EUV tools, 4F² as a one-time density gain that dead-ends — appear only in that article’s reader comments, not its reporting.
Chinese-language reporting goes further, and needs a caveat. A comprehensive piece by MyDrivers on October 27 says Samsung DS division CTO Song Jae-hyuk answered “yes” when asked at SEDEX 2026 whether Samsung is developing 4F², and that SK hynix’s CTO presented a 4F² vertical-gate platform and 3D DRAM roadmap at VLSI 2025. In English coverage those details exist only as TechInsights’ “still in their roadmaps”; the SEDEX and VLSI specifics currently trace to a single Chinese-language secondary source, so treat them as reported, not confirmed.
Our take
If you buy memory or spec hardware, nothing ships differently this quarter: 1γ-based product sells as before, and the next real density step is 1δ’s mid-20% gain in H2 2027. What changes is the expectation for where density comes from after 2028 — with the RAM shortage projected to run through 2028, Micron is betting its resources on lithography and wafer bonding rather than cell redesign. Price pressure has already reached consumers (memory now costs about 40% of a flagship phone’s BOM), and this roadmap shapes the supply curve those prices ride on.
For the industry watcher, the economics are the story: CXMT buys density with cell architecture, Micron buys density with lithography and wafer bonding, and DeBoer’s claim amounts to “litho is the cheaper buy.” Year-end, when CXMT’s 4F² RDIMM ships, the two bets get their first head-to-head data point.
The honest caveats sit on both sides: Micron’s own EUV history — a public “no,” followed by the latest adoption among the big three — shows a CTO’s webinar roadmap is not binding, 3D DRAM timing is undated, and the Samsung SEDEX and SK hynix VLSI details rest on one secondary Chinese-language source. Discount accordingly.
What to watch
- End of 2026: whether CXMT’s 4F² server DDR5 RDIMM ships on schedule — the first live comparison between the two routes.
- H2 2027: Micron 1δ volume production, testing the mid-20% bit density claim and the HBM5/vHBM/vEIM optimization.
- ζÅ/ηÅ nodes and the vHBM/vEIM vertical packages currently carry no production dates.